The present invention relates to a logic circuit conversion method for a digital logic circuit and a logic circuit design support device as a logic simulation device using the method.
In designing a computer system or LSI, detecting design logic deficiencies in the early stage by verifying the designed circuit by means of logic simulation is indispensable for shortening the time required for development.
On the other hand, with the recent increase in the integration degree of LSIs, LSIs and computer systems including them as constituent elements have increased in size and complexity more and more. The time required for logic simulation increases in proportion to the size of a circuit to be verified. The execution speed of a conventional logic simulator is about several clocks/sec with respect to a 100K gate circuit. Since the execution speed decreases in inverse proportion to the circuit size, a 1M gate circuit can only be processed at one clock/sec or less. Therefore, it takes much time to simulate a large-scale circuit. It is therefore difficult to perform design verification of a large-scale LSI by simulation using a sufficient long test vector. Considering a case wherein faults are found after an LSI is manufactured, in particular, the time required for correction, re-verification, development, and the like of design logic greatly increases, so does the cost. Under the circumstances, the designers demand higher-speed logic simulators.
A logic simulator is generally implemented by software. Many logic circuits to be verified by the logic simulator implemented by software are expressed by a language suited for the execution of software. For example, this language is a high-level language typified by the C language and an assembly language. When these languages are used, the value of each signal in a logic circuit is expressed by a variable, and the propagation of signals between logic circuits is described by signal assignment statements for the variables corresponding to the signals. The logic simulator executes these signal assignment statements in each simulation cycle to simulate signal processing in the circuit. Many logic simulators designed to receive logic circuit description described in a hardware description language (HDL) such as VHDL or Verilog-HDL have recently developed. Most of these logic simulators are designed to execute simulation after internally converting an input circuit description into a circuit description written in the C language or an assembly language. Such a simulator is intended to increase the simulation speed by devising a scheme of conversion to a computer language or optimizing a converted description. An increase in simulation speed intended by the logic simulator of this type depends on techniques in HDL processing schemes, but makes no contribution to a reduction in the processing amount required for simulation of a circuit.
An exhaust method is one of the logic simulation methods. In this method, signal assignment statements are sequentially executed in each simulation cycle. When a series of signal assignment statements is executed, it is checked whether the signal value of each signal is equal to that before the execution of corresponding signal assignments sentence. If any one of the signals has changed its signal value, a series of signal assignment statements is executed again. When all the signal values are determined by repeating this processing, the next simulation cycle starts.
In the exhaust method, however, even if an input signal value does not change, a series of signal assignments is executed, resulting in wasteful computation.
In a general logic circuit, signals occurring events are about 10% of the entire circuit. As described above, according to the exhaust method, since wasteful signal assignments increase in amount, simulation efficiency decrease.
A simulator based on an event-driven method has been developed as a logic simulator that solves the above problem. The event-driven method is a method of dividing a circuit into processing units having an appropriate size, and executing each processing unit only when any of corresponding input signals changes in value (event is occurred). A signal value is used for propagating a value between event execution units (processing units based on the event-driven method). The following is a general simulation execution sequence in the event-driven method.
(Step 1) A circuit is initialized.
(Step 2) A signal occurs an event.
(Step 3) An event execution unit to which each signal occurring an event is to be output is registered in an event queue.
(Step 4) The event execution unit registered in the event queue is evaluated. If a new event has occurred, the flow returns to Step 3.
(Step 5) The flow waits until the next event occurs, and returns to Step 2. If such an event does not occur, the sequence is ended.
When an each event execution unit is a small-scale circuit, a plurality of input signals to a given event execution unit are often evaluated in different event execution units. In such a case, if the event occurring timings of the respective input signals shift from the proper timings, a single event execution unit is repeatedly evaluated within one simulation cycle. This also increases the signal processing amount associated with the propagation of values between event execution units and the number of times an event execution unit is registered in an event queue or a registered event is extracted from the event queue.
As described above, if each event execution unit is a small-scale circuit, the processing amount required for simulation increases.
In general, a circuit described at a register transfer level (RTL) based on logical synthesis is constituted by many portions allowing parallel execution, which serve as processing function units each having an appropriate size. In addition, in describing a gate-level circuit, a small circuit element such as an AND or OR gate is handled as a unit. Therefore, a circuit described at the RTL or gate level requires a signal processing amount much larger than that required by a circuit at the behavioral level, which is not based on logic synthesis. It therefore takes much time to simulate such a circuit.
In this method, processing functions each having an appropriate size are regarded as event execution units, and a signal assignment in a given event execution unit is performed only when any of input signals to the corresponding processing function undergoes an event. Determination of a specific event execution unit to be executed in the current simulation cycle is managed by a time wheel or event queue.
As described above, according to the event-driven method, efficient simulation can be realized without performing wasteful signal assignment processing, unlike the exhaust method.
In the event-driven method, however, the overheads accompanying event management are heavy because the processing for event management is complicated. Event management is generally realized by using an event queue. In this case, the following operations are required:
a) extracting an event execution unit from the event queue; PA1 b) checking whether a given signal has occurred an event; PA1 c) scanning the event execution unit started by that signal; and PA1 d) registering the scanned event execution unit in the event queue.
To implement these operations, the program for the logic simulator using the event-driven method inevitably becomes complicated. In addition, the overheads associated with the time required for the execution of these operations are heavy.
Furthermore, if event execution units described in a logic circuit have inappropriate sizes, wasteful signal assignment processing is performed even in the event-driven method as in the exhaust method.
As described above, a logic simulator using the conventional exhaust method or event-driven method cannot always execute efficient simulation. This is because, the conventional logic simulator executes the signal processing flow described in an input logic circuit description, just as it is, resulting in overheads associated with the execution of unnecessary signal assignment processing. A circuit described at the RTL or gate level requires a signal processing amount much larger than that required by a circuit at the operation level, which is not based on logic synthesis. However, an increase in logic simulation speed in the prior art depends on techniques in an HDL processing scheme, but makes no contribution to a reduction in processing amount in a circuit description as in the above case. If, therefore, a circuit described at the RTL or gate level is to be simulated by the event-driven method, much time is spent to execute simulation.
In addition, the conventional logic simulator executes the signal processing flow in an input logic circuit description, just as it is, resulting in overheads that unnecessary signal assignment processing is executed.